This paper presents a hardware accelerator for image reconstruction in digital holographic imaging. The hardware accelerator executes a reconstruction algorithm which transforms the light captured on a digital image sensor into visible images. The reconstruction algorithm is based on a large two-dimensional FFT, which is a computationally demanding operation. Focus in this work is to maximize the computational efficiency and to minimize thememory transfer overhead to external SDRAM. This paper presents an efficient processing datapath and proposes a fast transpose unit and an interleaved memory storage scheme. The accelerator has been integrated together with a microprocessor, memory controller, sensor and monitor interface and has been verified on a custom design FPGA platform containing a Virtex-1000E device. The proposed architecture targeting a 0.13 ??m cell library achieves real-time performance with 20 frames per second.
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