Hardware accelerator for holographic image display

摘要

A hardware accelerator for a holographic image display system configured to display sequential subframes comprises an input buffer receiving image data from a source, and an output buffer to store generated holographic data prior to sending it to a spatial light modulator (SLM). The hardware accelerator also includes a processing module which generates the holographic data for each subframe based on the image data supplied from the input buffer. The processing module is controlled by a controller in order to provide a plurality of holographic subframes for display. The series of subframes are displayed sequentially in time such that they are perceived as a single reduced-noise image.