A 500 MS/s 6 bits delay line ADC with inherit sample hold

摘要

Analog-to-Digital Converters (ADCs) are essential blocks in digital signal processing systems, software defined radio receivers, and biomedical systems. This paper introduces a 6-bit Delay Line based Analog to Digital Converter (DL-ADC). This DL-ADC utilizes an inherited sample and hold technique to eliminate the dedicated power hungry sample and hold circuit. A prototype of the proposed DL-ADC is implemented in 65nm CMOS technology, where it consumes 1.8 mW and achieves a maximum SNDR of 35.5 dB with sampling rate 500 MHZ with a corresponding Figure of Merit (FOM) of 74.22 fJ/step.