首页> 外文会议>Electrochemical Society;Symposium on Silicon Compatible Emerging Materials, Processes, and Technologies for Advanced CMOS and Post-CMOS Applications >Process Dependent Optimization of Dielectric and Metal Stacks for Multilevel Resistive Random-Access Memory
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Process Dependent Optimization of Dielectric and Metal Stacks for Multilevel Resistive Random-Access Memory

机译:用于多级电阻随机存取存储器的电介质和金属堆叠的处理依赖性优化

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A HfO_2/Al_2O_3 bilayer structure for a two-terminal ReRAM device with the intention of having multiple resistance states as a function of compliance current (CC) after forming was evaluated Reduced power consumption was observed when the Al_2O_3 buffer layer was placed between the top electrode and the HfO_2 layer as compared to when it is embedded between the HfO_2 layer and the bottom electrode. Gradual resistance change capability was observed with varying CC The switching power requirement increases even if the Al_2O_3 buffer layer thickness was decreased when the buffer layer was near the bottom electrode. It was demonstrated that by modifying the deposition process of the top metal layer, the switching energy requirement could be altered.
机译:对于在顶部电极之间置于顶部电极之间时,评估了在形成后具有多重电阻状态的双端子RERAM器件的HFO_2 / AL_2O_3双层结构,以在形成的形成后,观察到降低功耗。 与嵌入HFO_2层和底部电极之间时相比,HFO_2层。 通过变化的CC观察到逐渐阻力变化能力,即使当缓冲层在底部电极附近时,切换功率要求也增加了Al_2O_3缓冲层厚度。 结果证明,通过修改顶部金属层的沉积过程,可以改变开关能量要求。

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