Low Power Latched Comparator Based Second Order Sigma Delta Modulator (SDM)

摘要

This paper presents the design of ±1.2V single bit second order continuous time (CT) SDM for audio application. The architecture uses low power latched comparator which consist of three stages i.e. preamplifier, kick back removal and latch circuit. Preamplifier dissipates less power and enhances the performance of SDM even at low voltage supply. Latch works as comparator and operates on two non overlapping phases which decides the sampling frequency and subsequently oversampling ratio (OSR) of the SDM modulator. Moreover preamplifier based latched comparator removes the need of D flip-flop which is previously used in conventional architecture resulting in less chip area. The proposed work also uses composite cascode operational amplifier (CCOA) for the design of active RC loop filter. In proposed work the comparator dissipates 80 μW power, which is designed using 180nm CMOS technology at ±1.2V power supply. The design achieves an OSR of 64 which corresponds to signal to noise ratio (SNR) improvement of 21 dB over the Nyquist converters. The proposed modulator achieves 80.75 dB SNDR with 25 kHz input signal.