An Analog-Digital Clock DLL Control Circuit Used for High-Speed High-Resolution Digital-to-Analog Converter

摘要

An analog-digital clock delay locked loop (DLL) control circuit is proposed to detect and adjust the analog-digital clock phase difference in real time in a 14-bit 2GSPS digital-to-analog converter (DAC). To achieve a reasonable analog-digital clock phase difference, a digitally controlled delay line (DCDL) should be able to provide a total clock delay up to 1024ps. Such fine control is realized by a control block tracking and maintaining the precise phase relationship between analog and digital clock domains. The control circuit is realized by designing a digital finite state machine (FSM) carefully. The proposed circuit is implemented in 0.18μm CMOS technology. Simulation results show that the proposed circuit performs well in various conditions in high speed data transmission applications.