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Analysis of electron transport in the nano-scaled Si,SOI and III-V MOSFETs: Si/SiO2 interface charges and quantum mechanical effects

机译:纳米Si,SOI和III-V MOSFET中电子传输分析:Si / SiO2接口电荷和量子力学效应

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The ITRS predicts that the scaling of planar CMOS(Complementary Metal Oxide Semiconductor)technology will continue till the 22 nm technology node [1] and a possible extension beyond is appealing [2].In this work,we investigate the effect of electron confinement [3] in nanoscaled transistor channels of 25 nm surface channel Si and 32 nm SOI(Silicon on Insulator)and 15 nm IF(Implant Free)III-V MOSFETs using a self-consistent solution of 1 D Poisson-Schrodinger equation [4,5].For simulation and development with accuracy of nano-scaled of 25 nmgate length Si MOSFET(Metal Oxide Semiconductor Field Effect Transistor),32 nm SOI Implant Free(IF)MOSFET,and 15nm Implant Free III-V MOSFET transistors,we investigated the bandstructure and quantum confinement effects occurring near the oxide-semiconductor interface in Metal-Oxide-Semiconductor(MOS)structure of Si MOSFET device.These investigation have been carried out using a self-consistent solution of 1D Poisson-Schrodinger equation across the channel of conventional Si/SOI/III-V MOSFET Transistors.To solve self-consistently 1D Poisson-Schrodinger equations across the channel of a conventional Si,SOI,and an Implant Free M-V MOSFETs to determine the conduction and valence band profiles,electron density,electron sheet density,eigenstate and eigenfunctions in these structures.We present the simulation results of conduction band profile,electron density(classical and quantum mechanical),eigenstate and eigenfunctions for Si,SOI and III-V MOSFET structures at two different bias voltages of 0.5 V and 1.0 V.For comparison,we calculate the electron sheet density(quantum mechanically)as a function of the applied gate voltages.
机译:ITRS的预测,平面CMOS的缩放(互补金属氧化物半导体)技术将继续直到22纳米技术节点[1]和可能延长超出是吸引人的[2]。在这项工作中,我们调查电子约束的效果[ 3]在25纳米表面沟道Si和32纳米的SOI(绝缘体上硅)和15nm的纳米级晶体管通道IF使用1 d泊松薛定谔方程的自相一致的溶液[4,5(种植体免费)III-V族MOSFET的]。对于模拟和开发具有纳米级25 nmgate长度的Si MOSFET(金属氧化物半导体场效应晶体管),32纳米的SOI种植体免费(IF)MOSFET的精度,和15nm的种植体自由III-V族MOSFET晶体管中,我们调查了在硅MOSFET device.These调查的金属 - 氧化物 - 半导体(MOS)结构的氧化物 - 半导体界面附近发生的带结构和量子限制效应已经进行了使用跨CH 1D泊松薛定谔方程的自相一致的溶液常规的Si / SOI / III-V MOSFET Transistors.To的annel解决跨传统硅,SOI,和植入物免MV MOSFET的沟道自洽1D泊松Schrodinger方程来确定导带和价带轮廓,电子密度,电子片材密度,本征态并且在这些structures.We本征函数的导带分布,电子密度(经典和量子力学)的模拟结果,本征态,并在两个不同的偏置电压的本征函数为硅,SOI和III-V族MOSFET结构0.5伏和1.0 V.For比较,我们计算出电子片材密度(量子力学)作为所施加的栅极电压的函数。

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