A novel high performance design of memory architecture using modified 4T CAM cell

摘要

In this paper, a novel modified 4T Content addressable memory (CAM) cell based Master-Slave Match Line (MSML) design for memory architectures is proposed. In memory architectures, match lines (MLs) and search lines (SLs) are main source of power consumption. The Proposed Modified 4T CAM cell based MSML design which reduces delay by 74%-95% with increases total power consumption and area compared with 4T CAM cell based MSML design.