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Performance Comparison of 4T, 3T and 3T1D DRAM Cell Design on 32NM Technology

机译:基于32NM技术的4T,3T和3T1D DRAM单元设计的性能比较

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In this paper average power consumption of dram cell designs have been analyzed for the nanometerscale memories. Many modern processors use dram for on chip data and programmemory. The major contributor of power in dram is the off state leakage current.Improving the power efficiency of a dram cell is critical for the improvement in average powerconsumption of the overall system. 3T dram cell, 4T dram and 3T1D DRAM cells are designedwith the schematic design technique and their average power consumption are compared usingTANNER EDA tool .average power consumption, write access time, read access time andretention time of 4T, 3T dram and 3T1D DRAM cell are simulated and compared on 32 nmtechnology.
机译:在本文中,已经针对纳米级存储器分析了德拉姆电池设计的平均功耗。许多现代处理器使用dram来存储片上数据和程序。 DRAM中功率的主要来源是关闭状态泄漏电流。提高DRAM电池的功率效率对于改善整个系统的平均功耗至关重要。使用原理图设计技术设计了3T DRAM单元,4T DRAM和3T1D DRAM单元,并使用TANNER EDA工具比较了它们的平均功耗。分别计算了4T,3T DRAM和3T1D DRAM单元的平均功耗,写入访问时间,读取访问时间和保留时间。在32 nm技术上进行了仿真和比较。

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