Variability and Performance on FDSOI Technology with Strained sSOI Substrate and SiGe Channel

摘要

Fully Depleted SOI (FDSOI) technology has been introduced at the 28nm node as a low-cost alternative strategy to FinFET. Developments on-going on 22nm and 14nm demonstrates the interest of this technology for CMOS scaling. In this talk, mismatch on FDSOI technology will be presented in order to list the main contributors of local variability. Back-bias impact on electrical parameters and variability will be discussed. Then, the effect of strain boosters on device variability and performance will be presented, including strained SOI substrates (sSOI), SiGe S/D and compressive/tensile CESL layer.