Impacts of Process Variability of Alternating-Material Self-Aligned Multiple Patterning on SRAM Circuit Performance

摘要

In this paper, we discuss a novel patterning technology to significantly reduce the edge-placement-error (EPE) effect by combining alternating-material (dual-material) self-aligned multiple patterning (altSAMP) and selective etching processes. Compared with the conventional single-material SAQP process, the altSAQP line features show a bi-modality characteristic in CDU and LWR data. Extensive circuit simulations are carried out to investigate SRAM performance in the presence of the altSAMP process variability. We also analyze the effects of supply voltage, fin-width and gate-length variations on FinFET-based SRAM circuit performance. Our simulation results show that improved device control with narrower fins helps to increase the static noise margin (SNM) in all SRAM cell designs we examined. Also, higher supply voltage is beneficial to the SNM performance. On the other hand, it is found that 6-T SRAM circuit design does not meet the six-sigma yield requirement when the minimum half pitch of SRAM devices is scaled down to sub-7nm. To reduce the SRAM circuit variability, we study an 8-T SRAM cell and show that it can significantly improve the SRAM performance.