Structural Design, Layout Analysis and Routing Strategy for Constructing IC Standard Cells Using Emerging 3D Vertical MOSFETs

摘要

As optical lithography and conventional transistor structures are approaching their physical limits, 3D vertical MOSFETs such as gate-all-around (GAA) nanowire MOSFETs and double-surrounding-gate (DSG) MOSFETs are two promising device candidates for post-FinFET logic scaling owing to their superior gate control and scaling potential. However, source, drain and gate of vertical GAA and DSG MOSFETs are located in different physical layers. Consequently, structural design of IC devices/circuits, layout arrangement and routing strategy for high-density vertical nanowires/interconnects are non-trivial challenges. In this paper, we first compare the device behavior of GAA and DSG MOSFETs. After that, the critical issues for constructing standard cells using 3D vertical GAA and DSG MOSFETs are discussed. We redesign the standard cells in NangateOpenCellLibrary for 5-nm node using these new device structures. Layout experimental results verify the functionality of the proposed standard-cell-layout design approach.