Research on the Low Power and Low Voltage CMOS Integrated Circuit Design Patterns and Methodologies

摘要

This paper presents the novel research on the low power and low voltage CMOS integrated circuit design patterns and general methodologies. With the integrated circuit technology to the rapid development of the deep sub-micron and nanometer order of magnitude, how to reduce the power consumption of the integrated circuit has become equally important problem with speed, area, power consumption constraints to further improve the performance of the chip, and increase the cost of the integrated circuit. A high level of integration and the application of high-speed device, especially in today's mobile devices and battery power equipment of the large-scale promotion, makes the power dissipation problem is becoming more and more prominent. Our research combines the literature list of reviews to propose the novel implementation paradigm for better performance.