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High performance Au/PZT/TiO_xN_y/Si MFIS structure for next generation ferroelectric memory applications

机译:高性能AU / PZT / TIO_XN_Y / SI MFIS结构用于下一代铁电存储器应用

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The Metal-Ferroelectric-Insulator-Semiconductor (MFIS) capacitors with thin 20 nm lead zirconate titanate (PZT) and titanium oxynitride (TiO_xN_y) buffer layer were fabricated by RF magnetron sputtering technique and characterized. TiO_xN_y as a buffer layer deposited for the first time for MFIS application at different thicknesses and fabricated structure was found to exhibit excellent electrical characteristics at 14 nm TiO_xN_y. Memory window of 0.4 V was found at low sweep voltage of ± 3 V which increases to 1.8 V at sweep voltage of ±14 V indicating multilevel data storage. Moreover the fabricated structure possesses low leakage current density of ~4 μA/cm~2 at 36 nm TiO_xN_y which increases to 12 μA/cm~2 at 4 nm TiO_xN_y at 5 V, reasonable limit. Furthermore, the fabricated structure possesses outstanding data retention capability at 14 nm TiO_xN_y; the high and low capacitance becomes constant after few seconds and clearly distinguishable for 1h and 30 min. This shows that proposed MFIS structure is suitable for high performance ferroelectric memory applications.
机译:用RF磁控溅射技术制造具有薄20nm铅锆钛酸钛酸盐(PZT)和氮氧化物(TiO_XN_Y)缓冲层的金属 - 铁电绝缘体 - 半导体(MFIS)电容器。 TiO_XN_Y作为在不同厚度和制造结构上首次沉积的用于MFIS应用的缓冲层,在14 nm tio_xn_y下表现出优异的电学特性。在低扫描电压为±3 V的低扫描电压下发现了0.4V的内存窗口,其扫描电压为±14 V表示多级数据存储的1.8V。此外,在36nm TiO_xn_y下,制造的结构具有低漏电流密度为4μA/ cm〜2的〜4μA/ cm〜2,其在5 V的4 nm tio_xn_y下增加到12μA/ cm〜2,合理的限制。此外,制造的结构在14 nm tio_xn_y下具有出色的数据保留能力;在几秒钟后,高和低电容变得恒定,并且可以在1H和30分钟内清楚地区分。这表明提出的MFIS结构适用于高性能铁电存储器应用。

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