Design of a CMOS Three-Stage Operational Amplifier for ALD

摘要

In this paper, a three-stage operational amplifier with low-power consumption for ALD has been designed. Based on TSMC 0.55μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that the proposed op-amp has more than 100dB open loop gain, meanwhile the static power consumption is less than 900μw. The circuit's phase margin is 103degrees, CMRR is 51dB and power supply rejection ratio is 57dB.