Optimization of interconnect delay based on Convex Optimization Technique

摘要

This paper discusses the Elmore delay optimization technique by varying the wire width. It also throws a light on various aspects which affects the interconnect delay. We will see that the delay minimization to zero will lead to a larger area covering interconnect wires, which will ultimately increase the area cost of IC. So 10 to 15% delay will give a good result keeping the IC size also in control. Optimization techniques if applied in IC designing, optimizes various other factors like the power dissipation and also the circuit compactness. So a good and robust optimization technique is required. In our work, we have employed the Convex Optimization Technique as it has the ability for finding the global optimum to a problem under any constraints with a less computational complexity.