Calibration Method for Increased Robustness against Non-Idealities in Discrete Time ΔΣ Modulators based on Current Conveyors

摘要

This paper presents several single and multi stage ΔΣ modulators designed in a 1V 90nm CMOS process. The important feature of these modulators is the replacement of the traditional opamp based integrators with integrators based on second generation current conveyor (CCII). The paper presents a calibration method to improve the robustness of the CCII based integrator against circuit non-idealities. In combination with the calibration algorithm, these modulators based on CCII offer several advantages over opamp based circuits. The integrator operates in open loop mode allowing increased bandwidth extraction from the circuit for less power consumption and removing any stability concerns due to lack of feedback. The virtual ground condition is enforced by a cross coupled connection at the inputs of the CCII similar to opamp to allow fast charge transfer from the sampling capacitor to the integration capacitor. The discrete time 2nd order and 4th order cascade ΔΣ modulator have SNDR of 72/69/61/65/62 dB and DR of 80/75/64/71/66 dB for signal bandwidths of 0.2/0.5/1/2/4 MHz at clock frequency of 40/80/80/120/120 MHz respectively.