METHOD AND APPARATUS FOR MANAGING ESTIMATION AND CALIBRATION OF NON-IDEALITY OF A PHASE INTERPOLATOR (PI)-BASED CLOCK AND DATA RECOVERY (CDR) CIRCUIT

摘要

A method for managing estimation and calibration of non-ideality of a Clock and Data Recovery (CDR) circuit. The method comprises A) selecting a first output path for calibration comprising at least a first Phase Interpolator (PI) of a plurality of PIs, at least one of a plurality of output-side programmable delay elements, an external delay element, at least one sampler, a first and a second external multiplexer, B) programming the output-side programmable delay element using a Digital Delay Control Code (DDCC), C) calibrating the external delay element until a given predetermined criterion based on an early-late detection method is met, D) upon satisfaction of the predetermined criterion, retaining a corresponding Digital External Delay Control Code (DEDCC) in the external delay element for subsequent use, E) selecting a second output path for calibration comprising at least a second PI of the plurality of PIs, the at least one of the plurality of output-side programmable delay elements, external delay element, at least one sampler, the first and second external multiplexers, F) calibrating the output-side programmable delay element until the given predetermined criterion based on the early-late detection method is met, G) upon satisfaction of the predetermined criterion, retaining the corresponding DDCC in the output-side programmable delay element for subsequent use, H) repeating the steps E-G for each of the remaining PIs such that the remaining output-side programmable delay elements are each separately calibrated, I) selecting a first input path for calibration comprising the at least first Phase Interpolator (PI) of the plurality of PIs, at least one of the plurality of input-side programmable delay elements, the external delay element, at least one sampler, the first and second external multiplexers, J) programming the input-side programmable delay element using the Digital Delay Control Code (DDCC), K) calibrating the external delay element until the given predetermined criterion based on the early-late detection method is met, L) upon satisfaction of the predetermined criterion, retaining a corresponding Digital External Delay Control Code (DEDCC) in the external delay element for subsequent use and M) assigning at least one value of a Binary Control Code (BCC) to select a unique phase in a given quadrant of a full phase cycle, N) calibrating the input-side programmable delay element until the given predetermined criterion based on the early-late detection method is met, O) upon satisfaction of the predetermined criterion, retaining the corresponding DDCBC in the input-side programmable delay element for subsequent use and P) repeating the steps M-O for each of the remaining unique phases in the inputs to the PI such that the remaining input-side programmable delay elements are each separately calibrated.