PACKAGE ASSEMBLY DESIGN KITS - THE TECHNOLOGY BRIDGE BETWEEN CHIP DESIGN AND WAFER-LEVEL MANUFACTURING AND ASSEMBLY

摘要

Design rules alone can only share the definitions of assembly and manufacturing requirements. However, a design rule cannot describe how it should be implemented into the design. The design rule relies on the interpretations of package designers to determine how to implement the rule into their own design tools for verification. The practice of sharing only design rules creates many delays and back and forth design iterations between the package designer and the outsourced semiconductor assembly and test (OSAT) provider. In contrast, package assembly design kits (PADKs) enable designers to perform design rule verification on their own designs prior to sending to the OSAT for the assembly of a successful wafer level (WL) package. Chip design companies and the OSAT have a very limited ability to exchange detailed design databases for Wafer Level Packaging (WLP). However, PADKs provide the ability to securely exchange advanced design rules and bridge the technology between chip design companies and the OSAT. This document will explore several different ways to share information between chip design companies and OSATs and will provide attendees with the benefits of sharing different styles of information for wafer level packages. Attendees can expect to leave with a broader understanding of how PADKs can significantly increase productivity, reduce cycle times, and limit the number of design iterations.