Fabrication and electrical characterization of Pd/TiO_2/n-Si MIS structure using TiO_2 film as insulator layer deposited by low temperature arc vapor deposition process

摘要

Fabrication and electrical characterization of a Pd/TiO_2/n-Si MIS structure have been reported in this paper. The TiO_2 layer has been deposited on n-Si by using low temperature arc vapor deposition (LTAVD) technique. The currentvoltage and capacitance-voltage characteristics were studied at room temperature (300 K) for sample devices with TiO_2 film annealed at different temperatures (450 to 550°C). The study reveals that the capacitance in the accumulation region has frequency dispersion at high frequencies which is attributed to leakage behavior of TiO_2 insulating layer, interface states and oxide defects. As-deposited film exhibits high level of interface states resulting in high leakage current density which can be reduced by an order of magnitude by post-deposition annealing. Different models of current conduction mechanism have been applied to study the measured data. It is found that Schottky–Richardson (SR) emission model is applicable at low bias voltage, Frenkel-Poole (FP) emission model at moderate bias voltages while Fowler–Nordheim (FN) tunneling dominates at higher bias voltages.