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PROCESS DEVELOPMENT CHALLENGES AND DESIGN OF EXPERIMENTS FOR CONFORMALLY COATED PRINTED CIRCUIT BOARD ASSEMBLIES

机译:流程开发挑战与实验的挑战与涂层印刷电路板组件的实验

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This study presents the various challenges involved in a large-scale automated spray conformal coating process for memory modules. A custom, in-house conformal coating process was improved based on the foundations laid out by prior process analyses and design study. The study showed support for acceptable levels of cleanliness, surface energy, improved wettability, and coverage of the coating material on the varied topography of the SODIMM (Small Outline Dual In-line Memory Module). During the development of the internal coating process, other issues emerged as process challenges. These issues included bearding, overspray, and foreign object debris (FOD) on module surface. These challenges were resolved by modifying the spray dwell-purge techniques and the fixture. In order to identify the optimum conformal coating parameters a general factorial experiment was conducted. Three factors were taken into consideration: coating material to thinner Mixing Ratio, Atomizing Pressure, and Micrometer setting. The factorial analysis used two replicates. Results indicate that optimum thickness can be obtained at a Mixing Ratio of 3:1, Atomization Pressure of 3.5psi, and at Micrometer setting of 400μm. Further tests were conducted to test the reliability of the coated module per IPC-HDBK- 830A, IEC, and other related JEDEC standards.
机译:本研究介绍了用于记忆模块的大规模自动喷涂保形涂布过程中涉及的各种挑战。基于现有过程分析和设计研究的基础,改善了定制的内部保形涂层工艺。该研究表明,对涂层材料的可接受,表面能,改进的润湿性和覆盖物的可接受水平的支持率(小轮廓双在线内存模块)的各种形貌。在开发内部涂层过程中,其他问题被出现为过程挑战。这些问题包括模块表面上的携带,过喷,外膜碎片(FOD)。通过修改喷雾停留吹扫技术和夹具来解决这些挑战。为了识别最佳的保形涂层参数,进行了一般阶乘实验。考虑了三种因素:涂层材料以更薄的混合比,雾化压力和千分尺设置。阶乘分析使用了两个重复。结果表明,最佳厚度可以以3:1,雾化压力为3.5psi的混合比率,微米凝固为400μm。进行了进一步的测试,以测试每个IPC-HDBK-830A,IEC和其他相关JEDEC标准的涂层模块的可靠性。

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