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HIGH DENSITY RDL TECHNOLOGIES FOR PANEL LEVEL PACKAGING OF EMBEDDED DIES

机译:嵌入式模具面板级包装的高密度RDL技术

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The ongoing miniaturization and functional heterogeneity in electronics packaging are pushing the demand for advanced substrate technologies. Highly integrated, advanced multi-chip packaging solutions combine application, logic and computing dies with memory or components for power management in a single package. A solution to achieve low fabrication costs is the close embedding of thin dies in IC Substrates based on large formats (600 × 600 mm~2), known from PCB fabrication. In a consortium of partners from industry and research advanced technologies for Panel Level Packaging (PLP) are developed. This paper will show the development of 5μm L/S RDL routing density and chips with 50μm bump pitch. Here, the 6×6 mm~2 dies are symmetrically embedded into an organic laminate matrix. A PCB core (100μm thickness) with very low coefficient of thermal expansion (CTE) containing laser cut cavities is used, acting as a frame layer. Besides mechanical and handling stability, the usage of such a frame offers the advantage of pre-integrating additional features like local fiducials, through vias or power lines by conventional PCB processes. Within that frame, the dies are embedded by lamination of an organic build-up film with 25 μm thickness equal to bump height. The chip contacts are then opened without the need of any micro via formation. Here a strong focus is set on RIE etching of the polymer material. Highly accurate measurement of the real die position is essential for the following processing. The formation of the redistribution layer (RDL) is done in a semi-additive process (SAP) utilizing sputtering technique and direct imaging (LDI). To achieve the fine pitch demands, an adaptive imaging process is applied. Therefore, a newly developed LDI machine is used to write structures in a 7μm photoresist. This exposure also combines the measurement data of the real die position and the adaption of the exposure artwork, in order to achieve highest registration quality.
机译:电子包装中正在进行的小型化和功能异质性正在推动对先进基板技术的需求。高度集成,先进的多芯片封装解决方案将应用,逻辑和计算模具与单个封装中的存储器或组件相结合,逻辑和计算模具。实现低制造成本的解决方案是基于从PCB制造中已知的大型格式(600×600mm〜2)的IC基板中的薄管芯的近距离嵌入。在工业和研究的合作伙伴联盟中,开发了面板级包装(PLP)的先进技术。本文将显示5μmL/ s RDL布线密度和碎片的开发,凸块间距为50μm。这里,6×6mm〜2管芯对称地嵌入有机层压板中。使用具有非常低的热膨胀系数(CTE)的PCB芯(100μm厚度),其作为框架层。除了机械和处理稳定性之外,这种框架的用途提供了通过传统PCB工艺通过通孔或电力线预先集成局部基准的附加功能的优点。在该框架内,模具通过层压有机堆积膜,其厚度等于凸块高度。然后将芯片触点打开而不需要任何微通过形成。这里,在聚合物材料的rie蚀刻上设定了强焦的重点。高精度测量真正的模具位置对于以下处理至关重要。利用溅射技术和直接成像(LDI),在半添加过程(SAP)中形成再分配层(RDL)的形成。为了实现细间距需求,应用自适应成像过程。因此,新开发的LDI机器用于在7μm光致抗蚀剂中写入结构。该曝光还结合了真实管芯位置的测量数据和曝光艺术作品的适应,以实现最高的登记质量。

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