The reconfigurable processors like FPGA are extensively used for cryptographic applications which have reduced the time to market of the hardware logic. This paper describes the high performance pipelined hardware implementation of RC5 algorithm in Xilinx Vertex II Pro FPGA with a 12-stage pipeline scheme that has achieved an encryption rate of 6.9 Gbps. The proposed design operates on 12 input data and a common key where each clock signal produces a partial single round encryption output. After 12 clocks cycles, the cipher text of the corresponding input data is derived at the output sequentially for every clock transition. The pipelined hardware was implemented and the efficiency was compared with the other versions of RC5.
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机译：像FPGA这样的可重新配置处理器广泛用于加密应用程序，这些应用程序将时间降低到硬件逻辑的市场。 本文介绍了Xilinx Vertex II Pro FPGA中RC5算法的高性能流水线硬件实现，具有12阶管道方案，该方案已经实现了6.9 Gbps的加密率。 所提出的设计在12个输入数据上运行和一个公共键，其中每个时钟信号产生部分单圆加密输出。 在12个时钟循环之后，相应输入数据的密度是按顺序导出的每个时钟转换的输出。 实施流水线硬件，并将效率与其他版本的RC5进行了比较。
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