FPGA SSD A NOVEL SSD ARCHITECTURE FOR FPGA BASED ACCELERATION

摘要

Disclosed is a system. The system includes: a processor to execute an application program; a memory storing data used by the application program running in the processor; an upstream interface to communicate with the processor; and a downstream interface to communicate with a storage device. The system also includes an acceleration module which is implemented by using hardware and includes an acceleration platform manager (APM-F) to execute an acceleration instruction. The storage device includes: an endpoint of the storage device to communicate with the acceleration module; a controller to manage operations of the storage device; storage to store application data for the application program; and a storage device acceleration platform manager (APM-S) to assist the acceleration platform manager in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a peripheral component interconnect exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.