Advanced packaging for future demands

摘要

Today's packaging is facing intensified challenges as modern electronic devices seek to combine a larger number of functions in a tight space in various environments. This results in chip designs determined by more complex circuitries and the use of fine pitch and micro bumps, as well as challenging interconnection properties. Selecting the best suitable interconnection technology is important. This paper gives an overview of advanced connection methods, like vacuum soldering, metal to metal diffusion bonding as well as nanowire bonding, predominantly used for flip chip packaging. During different trials, various dies characterized by high bump count (more than 1 million), fine pitch (down to 15 μm) and small bump diameter (down to 4 μm) were placed on a substrate using a semi-automated flip chip bonder. This whitepaper describes test procedures for these integration technologies and provides information on utilized process parameters and results.