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Design of the Digital Phase Meter with GPIB Interface Based on FPGA

机译:基于FPGA的GPIB接口设计数字仪表的设计

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Comparing with the traditional phase meter, the design of digital phase meter with GPIB interface based on FPGA have some advantages, such as the high date transmission rate, the simple circuit, short design cycle and the lower price. The principle of this design meets with the standard of IEEE488.2 and use Verilog HDL language to design every interface. Then compile simulate it in Quartus II. Finally download it to the FPGA experiment board to realize every function. It makes the date transmission more stable and reliable through the design of GPIB interface.
机译:与传统阶段相比,基于FPGA的GPIB接口的数字计量表的设计具有一些优点,如高日期传输速率,简单的电路,简单的设计周期和较低的价格。该设计的原理符合IEEE488.2的标准,并使用Verilog HDL语言来设计每个界面。然后在Quartus II中编译它模拟它。最后将其下载到FPGA实验板以实现每个功能。它通过GPIB接口设计使日期变速器更稳定可靠。

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