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Probing Strained Semiconductor Structures with Nanoscale X-ray Diffraction

机译:纳米级X射线衍射探测应变半导体结构

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The tailoring of strain distributions within semiconductor features represents a key method to enhance performance in current and future generations of complementary metal-oxide semiconductor (CMOS) devices. Although the impact of strain on carrier mobility in semiconductor materials was first investigated over 50 years ago [1,2], its implementation within the inversion layer of the channels in CMOS device channels has only occurred within the past decade. This includes the deposition of liner materials that possess significant values of residual stress [3]. Eigenstrained structures, deposited epitaxially within recesses on either side of the Si channel, can be used to induce either compressive strain in the channel region, by using materials that possess a larger lattice parameter than Si (e.g., SiGe)[4], or tensile strain, by using materials with a smaller lattice parameter (e.g., SiC). Because these methods generate heterogeneous strain distributions within the composite structure, it is critical to experimentally determine the distribution of strain across the current-carrying paths of the device and the surrounding environment. Real-space x-ray microdiffraction measurements represent the optimal method to perform direct, in-situ characterization of strain within crystalline materials at a submicron length scale [5,6]. The diffraction facilities at the 2ID-D beamline at Argonne National Laboratory's Advanced Photon Source were used for the x-ray microdiffraction measurements [6] with a nominal beam size of approximately 0.25 μm. Samples under investigation included both CMOS devices possessing embedded stressor materials and silicon-on-insulator (SOI) structures with overlying stressor features. The embedded stressor devices, fabricated from 55 nm thick SOI layers, contained Si_(1-x)C_x with a C content, x, of 1.1% in the source and drain regions, approximately 1.85 μm in length. Because C has a smaller lattice parameter than that of Si, the e-SiC structures possess in-plane tensile stress, which is transferred into the adjacent, 60 nm long SOI channel. To obtain a reference value for the unrelaxed SiC strain, square pads 200 μm in length, also consisting of heteroepitaxially deposited SiC, were characterized. Another set of SOI structures was fabricated possessing overlying stressor features, where compressively stressed Si_3N_4 films of approximately 105 nm thickness were lithographically etched to produce a matrix of rectilinear features possessing lengths of 2048 μm and widths ranging from 1 μm to 2048 μm.
机译:应变分布的半导体部件中的剪裁表示一个键的方法增强在互补金属氧化物半导体(CMOS)器件的当前和未来几代的性能。虽然应变对载流子迁移中的半导体材料的影响首先研究了超过50年以前[1,2],其在CMOS器件通道信道的反转层内执行仅在过去的十年内发生。这包括具有残余应力[3]的值显著衬里材料的沉积。 Eigenstrained结构,凹部内外延沉积在Si通道的任一侧,可以用于诱导在沟道区中任一压缩应变,通过使用具有比硅(例如,SiGe)的较大的晶格参数的材料[4],或拉伸株,使用的材料具有更小的晶格参数(例如,SiC)等。由于这些方法产生的复合结构内异质应变分布,重要的是通过实验来确定应变的整个周围环境中的设备的电流承载路径和分布。现实空间的x射线microdiffraction测量代表的最佳方法在亚微米尺度[5,6]执行直接,原位结晶材料内应变的表征。被用于X射线microdiffraction测量[6]具有大约0.25微米的标称光束尺寸在在阿贡国家实验室的先进光子源的2ID-d射束线衍射设施。在调查样品包括具有嵌入式应力材料和硅 - 绝缘体(SOI)结构与上覆应力源特征的CMOS器件。嵌入式应力器件中,从55纳米厚的SOI层制成,包含SI_在源区和漏区(1-X)C_x与C含量,X,1.1%,约1.85微米的长度。因为C具有比Si更小的晶格参数,则e-的SiC结构具有面内张应力,其被转移到相邻的,60nm的长SOI通道。以获得用于非松弛应变的SiC的基准值,方形焊盘200微米的长度,还包括沉积异质外延SiC构成,进行了表征。另一组SOI结构的制作具有上覆应力层的功能,其中,压应力大约105纳米厚的Si_3N_4膜光刻蚀刻,以产生具有的2048微米的长度和宽度范围从1μm至2048微米直线特征的矩阵。

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