The thesis of this paper is that as one seeks to define new device and interconnect systems that would either replace or supplement CMOS, it is important to evaluate these proposed new technologies in the context of their performance in an architectural framework. An energy barrier model is offered that is believed to be applicable for a broad class of devices and from which basic physics can be used to estimate device performance limits. The interconnect models used in this paper derive their inspiration from electron-based interconnect systems, and if other interconnect schemes are proposed, then performance limits similar to those offered in this paper would need to be derived to develop estimates for circuit-level performance.
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