SRAM Memory Cell Leakage Reduction Design Techniques in 65 nm Low Power PD-SOI CMOS

摘要

Whereas below 65 nm, Igidl and I_G become as important as ISTH in BULK technology, in PD-SOI technology ISTh is still the dominant current due to the floating body. Thereby, to overcome the leakage problem in PD-SOI, the main parameters to address are the body voltages of the cell transistors. It has been shown that the best results are obtained when letting the bit lines floating (FBL) and increasing the cell ground voltage (UVSS) or reducing the cell supply voltage (LVDD). Leakage reduction up to 80% is achieved.