首页> 外文会议>International Conference on Micro- and Nano-Electronics >Radiation-Hardening-by-Design with Circuit-Level Modeling of Total Ionizing Dose Effects in Modern CMOS Technologies
【24h】

Radiation-Hardening-by-Design with Circuit-Level Modeling of Total Ionizing Dose Effects in Modern CMOS Technologies

机译:通过现代CMOS技术的总电离剂量效果的电路级模拟辐射硬化设计

获取原文

摘要

Physical model of total ionizing dose (TID) effects previously developed and successfully verified by authors was embedded to BSIM3v3 model implemented using Verilog-A language. This tool is fully compatible with standard SPICE simulators and allows taking into account the electrical bias conditions for each transistor during irradiation.
机译:作者嵌入了先前开发和成功验证的全电离剂量(TID)效应的物理模型被嵌入到使用Verilog-A语言实现的BSIM3V3模型。该工具与标准Spice模拟器完全兼容,并允许考虑在照射期间每个晶体管的电偏置条件。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号