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TEACHING DIGITAL DESIGN IN A PROGRAMMABLE LOGIC DEVICE ARENA

机译:在可编程逻辑设备竞技场中教学数字设计

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Programmable logic devices have revolutionized the way in which digital circuits are built. FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices) have become the standards for implementing digital systems. FPGAs and CPLDs offer much higher circuit density, improved reliability, and fewer system components when compared with traditional digital design using discrete small-scale or medium-scale integrated circuits, all of which make programmable logic devices very attractive to the digital designer. However, these devices hide important details involved in understanding digital fundamentals, and the resulting hardware is really more of a computer-generated black box than it is a carefully crafted, fine-tuned design. Creativity in the design is less visible when using FPGAs or CPLDs, and designers are not rewarded as satisfyingly for "elegant" solutions to design problems. FPGAs and CPLDs implement solutions to digital design problems quickly and economically, both qualities that are important in an industrial setting. However, in an educational setting, the solution is not as important as understanding how the solution is reached, and these programmable devices automate and hide that process, making them less attractive as educational tools. Teaching digital design in a programmable logic device arena requires the instructor to inform students what is going on behind the scenes in the synthesis software. Otherwise, digital design degenerates into just another programming exercise, albeit using a hardware description language rather than traditional software languages. During Fall semester 2011, programmable logic devices were used for the first time as the basis for lab exercises in a second semester, advanced digital design laboratory at UMD, replacing design using discrete digital integrated circuits. The experience exposed some limitations imposed by the technology. For example, when circuits must avoid logic hazards (momentary "glitches" during transitions) as in asynchronous finite state machine design, FPGAs cannot be used properly, and CPLDs must be coerced into working by clumsily "fooling" the synthesis software. These specific digital circuit designs cannot be mapped cleanly to programmable devices without some innovative techniques. This paper reveals some of the author's experiences in adapting his digital design laboratory to the programmable logic device arena. Programmable logic devices, though attractive to the experienced designer, can be awkward to use in certain educational settings. Digital design instructors must be aware of their limitations. Instructors must find creative ways around the limitations, and must restrain themselves from being brainwashed by the glitz of FPGAs and CPLDs. This paper identifies techniques for maintaining the excitement and rewards of creative digital design within the confined restrictions of a programmable logic device arena.
机译:可编程逻辑器件彻底改变了建造数字电路的方式。 FPGA(现场可编程门阵列)和CPLD(复杂的可编程逻辑设备)已成为实现数字系统的标准。与传统的数字设计使用离散的小型或中型集成电路相比,FPGA和CPLD提供了更高的电路密度,更高的可靠性和更少的系统组件,所有这些都是使可编程逻辑器件对数字设计师非常有吸引力。然而,这些设备隐藏了理解数字基本原理所涉及的重要细节,由此产生的硬件更像是计算机生成的黑匣子,而不是精心制作的微调设计。使用FPGA或CPLD时,设计中的创造力不太可见,设计人员不会为设计问题的“优雅”解决方案而令人满意。 FPGA和CPLDS在快速和经济上实现了数字设计问题的解决方案,这两个质量在工业环境中都很重要。但是,在教育环境中,解决方案并不像了解如何达到解决方案,而这些可编程设备自动化和隐藏该过程,使其对教育工具的吸引力不那么有吸引力。在可编程逻辑设备领域的教学数字设计需要教师向学生通知学生在综合软件中的幕后发生的事情。否则,数字设计退化为另一个编程练习,尽管使用硬件描述语言而不是传统的软件语言。在2011年秋季学期期间,可编程逻辑器件首次使用了第二学期的实验室练习的基础,使用离散数字集成电路更换了设计。经验暴露了该技术施加的一些限制。例如,当电路必须避免逻辑危险时(在过渡期间的瞬时“毛刺),因为在异步有限状态机设计中,FPGA不能正常使用,并且必须将CPLDS转换为Clummany”愚弄“合成软件的工作。这些特定的数字电路设计不能清晰地映射到可编程设备,而无需一些创新技术。本文揭示了一些作者对可编程逻辑设备竞技场调整其数字设计实验室的经验。可编程逻辑器件,虽然对经验丰富的设计师有吸引力,但在某些教育设置中可以尴尬使用。数字设计教练必须意识到它们的局限性。教师必须在局限性周围找到创造性的方式,并且必须抑制自己被FPGA和CPLD的GLITZ被洗脑。本文确定了在可编程逻辑设备竞技场的狭窄限制内维持创新数字设计的兴奋和奖励的技术。

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