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COMMISSIONING OF THE IGP FEEDBACK SYSTEM AT DAΦ

机译:Daφ的IGP反馈系统调试

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The iGp (Integrated Gigasample Processor) is an innovative digital bunch-by-bunch feedback system developed by a KEK / SLAC / INFN-LNF joint collaboration. The processing unit can sample at 500 MHz and compute the bunch-by-bunch output signal for up to ~5000 bunches. The feedback gateware code is implemented inside just one FPGA (Field Programmable Gate Array) chip, a Xilinx Virtex-II. The FPGA implements two banks of 16-tap FIR (Finite Impulse Response) filters. Each filter is realtime programmable through the operator interface. At DAΦNE, the Frascati Φ-Factory, two iGp units have been commissioned in the April 2007. The iGp systems have substituted the previous betatron feedback systems. This insertion has been very fast and has shown no problems involving just a substitution of the old, less flexible, digital systems, letting unchanged the baseband analog frontend and backend. The commissioning has been very simple, due to the complete and powerful EPICS operator interface, working well in local and remote operations. The software includes also tools for analyzing post processor data. A description of the commissioning with the operations done is reported.
机译:IGP(集成Gigasample处理器)是由KEK / SLAC / INFN-LNF联合协作开发的创新数字束束反馈系统。处理单元可以以500MHz采样,并计算逐束输出信号,以便高达约5000串。反馈网件代码仅在一个FPGA(现场可编程门阵列)芯片内实现,是Xilinx Virtex-II。 FPGA实现了两个16-Tap FIR(有限脉冲响应)过滤器的银行。每个过滤器通过操作员界面进行实时可编程。在Daφne,弗拉斯卡蒂φ-工厂,两项IGP单位已在2007年4月委托。IGP系统已代替先前的Betatron反馈系统。这种插入非常速度,并且已经显示出涉及旧,更灵活,数字系统的替代,让基带模拟前端和后端替换的问题。由于完整和强大的史诗操作员界面,在本地和远程操作中运行良好,调试非常简单。该软件还包括用于分析后处理器数据的工具。报告了处理的调试的描述。

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