A 4-bit 1-GS/s ADC with a comparator-based successive folding (CSF) architecture is presented. Residue pre-charging and successive folding techniques are proposed for the CSF ADC to enhance quantization speed and achieve less complexity, leading to high power efficiency. Simulation results show that the ADC obtains a SNDR of 23.7dB at Nyquist input frequency and consumes 430μW from a 1V supply in 65nm CMOS, yielding a FOM of 34fJ per conversion step.
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机译：提出了具有比较器的连续折叠（CSF）架构的4位1-GS / S ADC。 CSF ADC提高了残留的预充电和连续折叠技术，以增强量化速度并实现更短的复杂性，导致高功率效率。仿真结果表明，ADC在奈奎斯特输入频率下获得23.7dB的SNDR，并在65nm CMOS中从1V电源消耗430μW，从而产生34FJ的FOM。
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