Quaternary CMOS Combinational Logic Circuits

摘要

Good Characteristics and advantages of multi-valued logic (MVL) electronic systems and circuits are created great interest for its practical implementation. This paper presents voltage mode quaternary CMOS circuit design using 90nm technology. Basic gates such as quaternary inverter, NMAX, NMIN and Quaternary multiplexer are designed and simulated. Low power consumption of 14 μW is observed at 2.2GHz with 1.2 V power supply. Circuits are verified using HSPICE simulations. The circuits described here are also suitable to be implemented in classical CMOS VLSI technology.