LOGIC CIRCUIT IN COMBINATION WITH PATH TRANSISTOR CIRCUIT AND CMOS CIRCUIT AND ITS COMBINATION METHOD

摘要

PROBLEM TO BE SOLVED: To obtain a logic circuit with a small area and excellent circuit characteristics such as a delay time and power consumption by combining the path transistor(TR) logic circuit and the CMOS logic circuit. SOLUTION: A binary tree is generated from a logic function and the path TR logic circuit is formed by mapping a path TR selector with two inputs, one output and one control input onto each node of the tree. In the path TR logic circuit, each of the path TR selectors one input of the two outputs other than the control signal input of which is fixed to a logical 1 or 0 and acting like a NAND or NOR logic is replaced with a CMOS gate such as a NAND or a NOR equivalent to its logic function and when the replaced CMOS gate provides a more optimum circuit characteristic (for example, a smaller area, or a smaller delay time or smaller power consumption), the path TR selector is replaced with a CMOS gate. Thus, the logic circuit with a small area, a small delay time and less power consumption is obtained.