With decreasing of feature size of VLSI designs, clock buffers are becoming quite huge. However, buffers often can’t be placed at ideal places because that traditionally clock network construction is performed after place-ment and at this time all cells are fixed. As a result, wire length and buffer numbers of clock net are increased. In this paper, a procedure called Buffered Clock Tree Aware Placement is proposed to consider clock network design in placement stage. Through register clustering and virtual clock tree construction, pseudo buffers are inserted in placement and deleted after that, so that white spaces are left for clock buffer insertion. Besides, registers in the same cluster are brought closer so that the performances of clock net, such as skew, delay and wire length, improves. The experiment results indicate an average of 22.40% improvement in skew, 7.26% improvement in delay and 2.10% improvement in wire length. Besides, the total distances of clock buffer mov-ing during overlap removing shows an average of 17.24% im-provement because of reserved white spaces.
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