With the increase in systematic defects at the 32/28nm nodes, it is now important to integrate design data into the fab environment to achieve high efficiency in defect management.; Introduction of design information helped identify weak pattern distributed randomly across the wafer.; Use of design information increased productivity in inspection recipe setup through accurate care-area definition and by permitting off-line setup. Design information enabled engineers to make best use of marginal pattern data to monitor their litho tools and to prioritize random defects based on their proximity to critical areas of device; Design integration has proven useful for both Memory and Logic device applications; Design-based setup and design-based binning are required for an effective implementation of the methods.
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