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VALIDATION OF THE POROUS-MEDIUM APPROACH TO MODEL INTERLAYER-COOLED 3D-CHIP STACKS

机译:验证模型层间冷却3D芯片堆叠的多孔介质方法

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Interlayer cooling is the only heat removal concept which scales with the number of active tiers in a vertically integrated chip stack. In this work, we numerically and experimentally characterize the performance of a three tier chip stack with a footprint of 1cm{sup}2. The implementation of 1OOμm pitch area array interconnect compatible heat transfer structures results in a maximal junction temperature increase of 54.7K at lbar pressure drop with water as coolant for 250W/cm{sup}2 hot-spot and 50W/cm{sup}2 background heat flux. The total power removed was 390W which corresponds to a 3.9kW/cm{sup}3 volumetric heat flow. An efficient multi-scale modeling approach is proposed to predict the temperature response in the complete chip stack. The experimental validation confirmed an accuracy of +/-10%. Detailed sub-domain modeling with parameter extraction is the base for the system level porous-media calculations with thermal field-coupling between solid - fluid and solid - solid interfaces. Furthermore, the strength and weakness of microchannel and pin fin heat transfer geometries in 2-port and 4-port fluid architectures is identified. Microchannels efficiently mitigate hot spots by distributing the dissipated heat to multiple cavities due to their low porosity. Pin fins with improved permeability and convective heat dissipation are advantageous at small power map contrast and aligned hot spots on the different tiers. Large stacks of 4cm{sup}2 can be cooled sufficiently by the 4-port fluid delivery architecture. The flow rate is improved four times compared to the 2-port fluid manifold. The non-uniformity of the flow in case of the 4-port demands a more careful floor-planning with hot spots placed in the chip stack comers. This is especially true in case of communicating heat transfer geometries such as pin fin structures with zero fluid velocity in the stack center. This large velocity contrast can be reduced by the implementation of non-communicating microchannels.
机译:中间层冷却是唯一的散热概念,其具有垂直集成芯片堆叠中的有源层的数量。在这项工作中,我们在数值上和实验地表征了三层芯片堆叠的性能,具有1cm {sup} 2的占地面积。 1OOμm间距区域阵列互连兼容传热结构的实现导致LBAR压力下降的最大结温增加54.7k,水为250W / cm的冷却剂2个热点和50W / cm {sup} 2背景热通量。除去的总功率为390W,其对应于3.9kW / cm {sup} 3容量热流。提出了一种有效的多尺度建模方法来预测完整芯片堆叠中的温度响应。实验验证证实了+/- 10%的准确性。具有参数提取的详细子域建模是系统级多孔介质计算的基础,具有固体 - 流体和固体界面之间的热场耦合。此外,鉴定了2端口和4端口流体架构中微通道和销鳍传热几何形状的强度和弱点。微通道由于其低孔隙率,通过将耗散的热量分配到多个空腔来有效地减轻热点。具有改善的渗透性和对流散热具有改善的销翅片在小功率图对比度并对不同层上的热点对齐。通过4端口流体输送架构可以充分冷却4cm {sup} 2的大堆叠。与2端口流体歧管相比,流速提高了四次。在4端口的情况下,流动的不均匀性需要更加谨慎的造型计划,其中热点放置在芯片堆叠中。在连通传热几何形状的情况下尤其如此,例如在堆叠中心中具有零流体速度的销翅片结构。通过实施非通信微通道,可以减少这种大型速度对比度。

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