Timing yield estimation of digital circuits using a control variate technique

摘要

The Monte-Carlo (MC) technique is a traditional solution for reliable yield analysis, and in contrast to probabilistic methods it can account for any complicated timing and process variation models. However, a precise analysis that involves a traditional MC-based technique requires many simulation iterations, especially for the extreme quantile values. In this paper, a new yield estimator is developed for the timing yield of digital circuits based on an auxiliary (control) variable which is formed by extracting the delay equation of the nominally critical path. The superiority of the proposed technique is studied and verified against the crude-MC and the advanced sampling techniques, Latin Hypercube Sampling and Quasi-MC. The technique shows significant (2X to 30X) runtime improvement over the crude-MC by reducing the required number of iterations to achieve a maximum confidence interval.