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Yield evaluation of analog placement with arbitrary capacitor ratio

机译:采用任意电容比的模拟放置的产量评估

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Capacitance mismatch can be generally attributed two sources of errors: random mismatch and systematic mismatch. Random mismatch is caused by the process variation, while systematic mismatch is mainly due to asymmetrical layout and processing gradients. Common centroid structure may reduce the systematic mismatch, but not the random mismatch. Based on spatial correlation model, this study derives the relationship among correlation, mismatch, and variation of capacitance ratio. Results show that the placement of unit capacitance array with higher correlation results in lower mismatch and lower variation of capacitance ratio. For any arbitrary capacitance ratio, i.e., more than two capacitors, if the summation of correlation coefficients for all capacitance pairs is defined as ??index??, the placement with higher index results in higher yield, where the yield is defined as the ratio of the acceptable designs over the sample size. In other words, one can find a near-optimal placement which has better yield by using the simple calculation of index, instead of the complicated circuit simulations.
机译:电容不匹配通常归因于两个错误源:随机不匹配和系统不匹配。随机不匹配是由过程变化引起的,而系统不匹配主要是由于不对称的布局和处理梯度。常见的质心结构可以减少系统不匹配,但不是随机不匹配。基于空间相关模型,该研究得出了相关,失配和电容比的变化之间的关系。结果表明,具有较高相关性的单元电容阵列的放置导致较低的不匹配和电容比的更低变化。对于任何任意电容比,即多于两个电容器,如果所有电容对的相关系数的总和被定义为索引??,具有更高指标的放置会导致较高的产量,其中产量被定义为比率在样本大小上可接受的设计。换句话说,可以通过使用简单的索引计算来找到近最优放置,而不是复杂的电路模拟。

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