Impact Ionization and Freeze-Out Model for Simulation of Low Gate Bias Kink Effect in SOI-MOSFETs Operating at Liquid He Temperature

摘要

A 0.4μm p-channel silicon-on-insulator (SOI) metal-oxide-field-effect-transistor (MOSFET) is measured at 300K and 4K. Finite difference two dimensional numeric device simulations are performed at these temperatures to provide physical insight about the mechanisms that lead to the observed cryogenic effects at liquid Helium temperature. The MOSFET subthreshold slope is measured as 88mv/dec at 300K and is observed to have a drain bias dependence at 4K ranging from 30mv/dec at low source-to-drain (V{sub}(SD)) voltage (0.05V) to 10mv/dec at high V{sub}(SD) (3.3V). A kink in the current is furthermore observed at low gate bias (1.35V) and drain bias above 2V. The numeric simulations indicate that incomplete ionization of dopants at cryogenic temperatures and impact ionization significantly affect the device behavior in the subthreshold region of operation at 4K. Specifically, for a low source-to-gate (V{sub}(SG)) bias (V{sub}(SG)=1.35V, which is near subthreshold) the former affects the base current level, and the latter along with the incomplete ionization gives rise to a current kink for high drain biases (V{sub}(SD)>2V). The simulation techniques to handle the numerical challenges related to device modeling at 4K are also presented.