At-Speed scan is a key technique in modern IC testing. One of its drawbacks, with respect to functional tests, is its excessive power consumption leading to voltage drop and frequency degradation. This paper discusses the frequency and power correlation between At-Speed Scan and functional tests. The influence of voltage drop on frequency is demonstrated by silicon measurements and supporting simulation results. The localized nature of the voltage drop as well as impedance component analysis are presented. Additionally, the need for power aware scan patterns is also discussed. Suggestions for achieving a higher correlation between At-Speed scan and functional patterns, with respect to power consumption, are offered.
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