High Density Interconnect (HDI) and micro-via in pads technologies continue to facilitate the development of smaller, lighter, more powerful electronics by enabling finer pitch I/Os, thinner circuit boards, and higher routing densities. However, increases in Printed Circuit Boards (PCBs) density and the need for higher electrical performance have resulted in several design challenges. Some of these unique challenges for both PCB fabricators and assemblers are related to the micro-via in pads to the organic integrated circuit (IC) substrate. On the assembly side, chronic SMT defects with conventional micro-via in pads are the high occurrence of tombstoning and considerable voiding that can lead to low yields and increased product costs. Although tombstoning and voiding in typical solder joints have been studies extensible, very little work has been done on the emerging micro-via applications which appear to be more prone to tombstoning and voiding problems. In this study, tombstoning behavior was primarily studied and potential factors such as micro-via in pads structure, reflow profile, reflow atmosphere, solder paste and paste deposit volume which may affect tombstoning in micro-via of lead-free solder joints were investigated.
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