COST REDUCTION OF WAFER LEVEL PACKAGING BY USING ESTABLISHED MATERIALS FROM NON-ELECTRONICS INDUSTRIES

摘要

Solid state imagers are being incorporated in an ever-expanding diversity of products. The drivers engendering this trend are decreasing cost coupled with physical size reduction and improved reliability. Historically, semiconductor device packaging has been able to absorb the cost of expensive materials provided they delivered the necessary performance. The consumer demand for vast quantities of camera modules at very low price is forcing a search for new packaging technologies utilising radically different materials. This paper will present a new wafer-level chip size package that comfortably exceeds mobile phone and automotive reliability standards. In this technology the image sensor is protected from contamination using a cover glass from the initial stage of processing. The electrical contacts on the front face of the silicon are connected to a ball grid array on the rear surface of the package, making it suitable for standard surface mount assembly. The final package thickness is approximately half that of the original silicon wafer. A key element of the package is that it is fabricated using a material produced in extremely high tonnage for an entirely different industry and purpose and therefore, is significantly cheaper than anything comparable made specifically for semiconductor applications.