Compliant WLP for Enhanced Reliability-(PPT)

摘要

Developed a complaint wafer level packaging (WLP) for large die through FEA modeling and experiment. Modeled and verified electrical performance for DDR memory applications. Demonstrated a reliable WLP structure mounted on PCB board. Demonstrated a WLP structure testable without socket interposer. Electrical verification of WLP post structure for low cost test/BI is in progress.