Challenges and solutions for Chip Package Interaction

摘要

Chip package interaction (CPI) has gained a lot of importance in the microelectronics industry due to the increased number of reported reliability problems at integrated circuit (IC) level. During package assembly of Cu/low-k chips and subsequent reliability tests or even under operation conditions, the thermo-mechanical deformation of the package can be directly transferred to the Cu/low-k interconnect, inducing large local stresses to initiate and drive cohesive and/or adhesive crack formation and propagation (Figure 1). The impact of CPI on the reliability of BEOL has recently generated extensive interest, especially for the advanced technology nodes. To assure reliability during chip packaging and under field conditions, the semiconductor industry needs reliable, reproducible testing methods and strategies to monitor the mechanical stability of low-k, not only for thin films, but also for complete interconnect stacks. This work discusses the extensive development work that was performed at imec to mitigate CPI risks for the BEOL during IC package assembly.