Nm-System's Jitter Resonance induced by PDN noise of toggling on-die Logic

摘要

This work presents the research of undesirable effects revealed in nm-devices: on-die signals' timing variations (Jitter) due to switching of the internal die logic. The research shows that the generated Jitter might dominate all other Jitter components and limit achievable nm-devices speed. We demonstrate that nm-system experiences a Jitter resonance which happens at different frequency compared to the power delivery network (PDN) noise resonance. The methodology developed here enables measurement of the PDN-related Jitter without using on-chip measurement IPs. The relationships between PDN noise and Jitter resonance frequencies are established. Using these relationships we developed method for evaluation of PDN noise resonance "from die side" through Jitter measurements. The methodology of power noise modeling also developed and used for analysis of proposed methods of PDN resonance and system Jitter evaluations. Different ways for reducing PDN-related Jitter effects are also discussed.