A CML-CMOS logic level converter with low supply noise induced jitter

摘要

The bias current Ibias controlling the current-switching portions 106,108 of a CML to CMOS logic level converter varies inversely with the supply voltage so that the decreased propagation delay of the output CMOS voltage-mode buffer is counteracted by an increased propagation delay in the predriver 108. Jitter in the output signal due to supply noise is reduced without requiring extra components in the converter. There is thus no loss in bandwidth due to the capacitance of these components. The drain-source resistance of the earthed gate PMOS transistor in the bias stage 102 reduces as the supply voltage increases, leading to a fall in bias current.