Back-End Methodology and Techniques for a Multi-Protocol Mixed Signal IP Design

摘要

ASIC I/Os have been evolving from relatively slow parallel interfaces to high-speed serial links. Examples include PCI to PCI Express (2.5 Gbps), ATA to SATA (1.5-3 Gbps), and SCSI to SAS (1.5-3 Gbps). Additionally, the XAUI interface, which operates at 3.125 Gb/s, has gained popularity as an ASIC interface. This evolution has created a difficult design problem for ASIC manufacturers that is increasingly being solved by purchasing rather than developing the required I/O IP. While the analog design aspects of such a development are daunting there is an equally difficult problem for the digital backend. In this paper we will focus on the back-end challenges and solutions in development of a physical layer, mixed-signal IP (PHY) that supports three standards: PCI-Express, SATA, and XAUI. The PHY is currently designed in TSMC 90 nm and 130 nm, specifically TSMC90G, TSMC90GT, TSMC130G, TSMC130LV, and TSMC130LVOD recently developed by Synopsys' Hillsboro PHY Group and design services business unit.