A novel assertion based Methodology to verify mixed signal SOC designs in Digital and Mixed signal verification flow

摘要

This paper describes a method to verify complex analog circuits. The behavioral models of the complex analog circuits are written in VHDL structural style. The VHDL based assertions are written for checking the behavioral models of the complex analog circuits. The assertions were later transformed into Verilog-A checkers for the actual netlist of the complex analog circuits. The netlist is taken from the actual design which then includes the Verilog-A checkers at selected places. These assertions are verified manually after they are actually asserted for specified condition.